1. Field of the Invention
One embodiment of the present invention relates to a memory device or a semiconductor device which includes a memory cell capable of holding data temporarily even when supply of power is stopped. One embodiment of the present invention relates to an electronic device which includes the memory device or the semiconductor device.
Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, a method for driving any of them, and a method for manufacturing any of them.
2. Description of the Related Art
Memories such as an SRAM and a DRAM have already been used in a variety of electronic devices. For example, an SRAM or a DRAM is widely used as a cache memory. A cache memory is used in a central processing unit (CPU), a hard disk drive (HDD), a solid state drive (SSD), or the like. A cache memory is provided to input or output data to a logic circuit quickly.
Current electronic devices are required to reduce power consumption. For example, there is power gating, which allows reduction in power consumption in such a manner that power supply to circuits which are not used is stopped and power is supplied to circuits which are used as appropriate in an electronic device including a plurality of circuits.
In contrast, since an SRAM and a DRAM are volatile memories, data is erased when the power is turned off. Therefore, when power gating is performed on an SRAM or a DRAM, data stored in the SRAM or the DRAM is erased; therefore, data needs to be written again after the power is turned on, leading to the delay of the response. For this reason, a nonvolatile memory is required.
Although an example of nonvolatile memories includes a flash memory, response speed of a flash memory is low. As a novel memory, a memory using an oxide semiconductor has been proposed.
The off-state current of an FET using an oxide semiconductor is extremely low. For example, the off-state current per micrometer of the channel width at 85° C. is less than or equal to 100 yA (1 yA (yoctoampere) is 1×10−24 A). Thus, a memory element which can hold data for a long period can be formed using an oxide semiconductor FET and a capacitor (e.g., Patent Document 1).
Even if the retention period of a memory using an oxide semiconductor is as long as over 10 years, a so-called refresh operation, in which charge is stored in a capacitor of a memory again, is in demand in order to achieve a longer period of data holding.
A technique of controlling the threshold value of an oxide semiconductor FET is still under development. In the case where the threshold value is shifted in the negative direction, the off-state current is increased at Vg=0 V. Owing to the shift in the threshold value, a data retention period is shortened. Therefore, a refresh operation in which charge is stored in a capacitor of a memory again is required for lengthening a data retention period.
There is a method in which through regular refresh operations, charge is stored in a capacitor of a memory using an oxide semiconductor again so that a data retention period is lengthened (e.g., Patent Document 2).